The present invention relates to a semiconductor device and a method for manufacturing it, and particularly relates to a semiconductor device using diffusion layers, as bit lines, provided in a semiconductor substrate and a method for manufacturing it.
Recently, semiconductor devices can reduce the area of a memory cell array if word lines and bit lines are intersected with each other with an insulating film interposed and a memory cell is formed at each of the intersections, and therefore, such semiconductor devices have grown in importance in association with miniaturization of semiconductor devices.
Such a conventional semiconductor structured as above and a method for manufacturing it will be described below with reference to FIG. 10A to FIG. 10C (see Japanese Patent Application Laid Open Publication No. 2002-050705A, for example).
First, as shown in FIG. 10A, there are provided a plurality of bit line diffusion layers 102 formed in a row direction in the upper portion of a semiconductor substrate 101 made of silicon (Si), a bit line insulating layer 103 formed on each of the bit line diffusion layers 102, a plurality of gate insulating films (not shown) formed on the semiconductor substrate 101 between the respective adjacent bit line diffusion layers 102, and a plurality of word lines 104 formed in a column direction on the bit line insulating films 103 so as to intersect with each bit line diffusion layer 102 and each gate insulting film. Herein, the row direction means the direction parallel to the paper of the drawing and the column direction means the direction perpendicular to the paper. The bit line diffusion layers 102 are thermal diffused to extend outwards of the end portions of the bit line insulating films 103.
Next, as shown in FIG. 10B, a plurality of connection diffusion layers 105 for electrically connecting the bit lines 102 to, for example, another circuit are formed using a dopant indicating the same conductivity as that of the bit line diffusion layers 102 so as to include the end portions of the bit line diffusion layers 102. Thus, overlapped connection parts 105a connected to the bit line diffusion layers 102 are formed.
Subsequently, as shown in FIG. 10C, a silicide layer 106 is formed on each of the word lines 104, the overlapped connection parts 105a, and the connection diffusion layers 105.
In the above conventional semiconductor device and the method for manufacturing it, however, the area (plane area) of the overlapped connection parts 105a must be increased in order to reduce the diffusion layer resistance of the overlapped connection parts 105a. This requires the bit line diffusion layers 102 to be thermal diffused largely after the formation of the bit line insulating films 103 on the bit line diffusion layers 102. Thermal treatment for largely diffusing the bit line diffusion layers 102 expands the diffusion layers in the memory cells excessively, inviting difficulty in miniaturization.